These FPGA/ASIC IP cores are designed using advanced techniques leading to ultra-low gate count utilization and amazing latency performances.
The high-performance Ethernet MAC & PCS IP cores are based on a unified Verilog code solution that scales from 1-Gbps to 100-Gbps data rates. The cores optionally include Reed Solomon FEC RS (528, 514, 10) with FEC bypass and error correction bypass capabilities.
Best-in-class performances in all categories and include some unique differentiators :- Significant improvement in gate count and resource utilization performances
- Ultra-low wire-to-wire latency for all options
- Unified code solution supporting multiple rates, 1-, 10-, 25-, 40- and 100-Gbps
- Fully integrated MAC, PCS, and optionally RS-FEC solutions
- High timing margin of > 20% on mid-speed grade FPGA devices
- High scalability and flexibility where same code and documentation is valid for all rates
- Fully configurable statistics vector and collector on MAC, PCS, and RS-FEC
We can discuss your project requirements together.
