Ultra-low latency FPGA Framework
for SmartNIC
FPGA DEVELOPMENT KIT (FDK) DESIGNED FOR HIGH-FREQUENCY TRADING, HIGH-PERFORMANCE COMPUTING, AND NETWORK APPLICATIONS.
Our product
ULL FPGA Framework
Innovatively resolve the trade-off between speed and flexibility in ultra-low latency systems.
Our ULL FPGA Framework is designed to enable real-time access and response to fast-moving data, ensuring ultra-low latency and high performance in High-Frequency Trading (HFT), High-Performance Computing (HPC), and networking.
Typical Latency Performances:
What is OT - ULL FPGA Framework
Hardware and software development framework designed to efficiently build ULL FPGA applications
The Orthogone Ultra Low Latency FPGA Framework consists of programmable, high-performance FPGAs and software development frameworks optimized for ultra-low latency applications. Our solution integrates seamlessly with different platforms to meet specific acceleration requirements.
Unleash the potential of Orthogone's ULL FPGA Framework
SOLUTION BRIEF – FPGA Solutions for Ultra-low Latency SmartNIC
Quickly develop the ultimate portfolio of flexible FPGA and software applications
Typical use cases
Technical description and features
Quickly develop the ultimate portfolio of flexible FPGA and software applications
The FPGA Development Kit (FDK) includes a complete suite of IP cores, an end-to-end FPGA development environment, and a comprehensive software framework.
All FPGA IP cores achieve ultra-low latency while maintaining a reasonable timing margin and preserving critical FPGA resources for on-chip computational acceleration.
With its standard interfaces and highly customizable FPGA cores, the framework easily supports adding features and evolves according to your needs while maintaining exceptional performance.
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- ULL MAC/PCS: Ultra-low latency Ethernet MAC/PCS
- ULL TCP/IP: Implements a full TCP/IP stack in FPGA with ultra-low latency performances
- ULL UDP/IP: Implements a full UDP/IP stack in FPGA with ultra-low latency performances
- ULL PCIe DMA: Ultra-low latency DMA controller to move data between FPGA and host memory rapidly over PCIe interface
- FPGA RTL design for lowest possible latency:
- MAC/PCS
- TCP/IP Offload Engine
- UDP/IP Offload Engine
- PCIe DMA Controller
- Supports Xilinx UltraScale+ FPGA
- Supports Xilinx Alveo FPGA platforms
- FPGA simulation and verification environment
- Linux CentOS distribution
- Kernel bypass for optimized data path
- Ultra-low latency C/C++ API with zero-copy optimized path
- Advanced network statistics
- Test and debug applications
FPGA Development Kit
- Encrypted FPGA IP cores
- Reference design examples
- Product datasheet and user guides
- ETest bench use case
- FPGA build scripts
- Test and debug applications for latency/throughput measurement
Software Framework
- C/C++ API with zero-copy optimized path
- FPGA Communication & IP core management via drivers & C/C++ libraries
- Product documentation
Pricing model and support
As experts in developing and customizing low-latency FPGA/ASIC IP cores, we also offer integration and post-sales services to support your internal team.
FLEXIBILITY IS THE KEY WORD HERE
Several pricing options are available depending on your needs and your platforms.We know how to adapt to your:
- needs
- business
- budget
Our ecosystem of technology partners
Ready for the next level? Contact us
FPGA/ASIC IP Integration and customization
We also support the continued development of advanced technologies by designing custom FPGA development solutions for your unique needs.
Through our design flow process, intellectual property portfolio and advanced verification process, we provide complete solutions tailored to your project.
