Digital Mammography Detector

Universal and highly versatile platform based on FPGA with embedded ARM processor

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Developers of the Seemingly Impossible

The Challenge

Develop a digital mammography detector where medical certification and qualification typically increase development costs, and time to market.

Client: Analogic – NASDAQ: ALOG

Location: MONTREAL, QC, CANADA

Integrate flexibility into the design to extend the product lifecycle.

Implement technologies that favor re-use in multiple applications.

François Boucher, Director of Engineering

For over 40 years Analogic has created markets by anticipating and solving some of the world’s most complex medical and engineering challenges in areas such as computed tomography (CT), ultrasound, digital mammography (DM), and magnetic resonance imaging (MRI).

THIS IS HOW WE DO IT

To overcome these challenges, Orthogone implemented a universal, highly versatile platform based on FPGA with embedded ARM processors. The design favors technology re-use across a wide range of product lines and multiple applications.

The system was also architected to allow SW engineers and researchers to easily develop and implement their new, constantly evolving image processing algorithms without having to know anything about the FPGA implementation.

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The Breakthrough Innovation

The Result

Through innovative design and use of technology, Orthogone was able to develop a solution that has the versatility and ease of use required to maintain its competitive edge over extended product life cycles with full production expected for 2018.

HARDWARE DESIGN

ELECTRONIC DESIGN OF A HIGH-SPEED, ULTRA-LOW NOISE PRINTED CIRCUIT BOARD (PCB), INCLUDING:

  • Hardware and mechanical design concept and architecture
  • Low-noise hardware design of analog circuits
  • Hardware design based on Xilinx UltraScale+ MPSoC and multiple peripherals (DDR-4 memory banks, USB Type-C, sensor interfaces, etc.)
  • Post-layout simulations of high-speed mixed-signal circuits
  • FPGA Design of a highly programmable image processing engine. The system is partitioned to easily decouple the SW based algorithms development from the highly optimized HW acceleration performed by the FPGA fabric
  • FPGA Hardware acceleration of image processing algorithms

SOFTWARE DESIGN

  • Board Support Package and device drivers (Xilinx MPSoC, USB Type-C, I2C, QSPI Flash, DMA transfers, SW/FW upgrades, etc.)
  • OS Platform Supported: Linux, Mentor Embedded Linux, Nucleus RTOS
  • Software development and optimization of fully HW accelerated image processing functions (from acquisition sensors to external communication interface, e.g. Host PC)

Technology
 used
  • Xilinx MPSoC UltraScale+
  • Ultra-low noise analog design
  • USB Type-C
  • HW Accelerated (FPGA) Image Processing Algorithms

Success is in the execution

Find out why 80% of our product development projects are from repeat customers.

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Our location

200-1425 Trans-Canada Highway
Dorval, Québec, Canada
H9P 2W9

So, what's your challenge?

So, what's your challenge?

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