Ultra-low Latency 
Ethernet MAC

One-stop solution for custom silicon IP

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Developers of the Seemingly Impossible

Licensable Intellectual Property for FPGA, ASIC or ASSP Designs

Industry leading solutions for latency CRITICAL ETHERNET APPLICATIONS

Ultra-low latency performances, ultra-low gate count & resources utilization

Based on a unified architecture where all rates and options are supported

Excellent timing margin and including a rich set of standard and advanced features

Unified Verilog source code and UVM environment

1G

Ultra-low latency 1G Ethernet mac and pcs

10G

Ultra-low latency 10G Ethernet mac and pcs

25G

+RS-FEC

25G Ethernet MAC & PCS
+ RS-FEC

40/
100G

+RS-FEC

40/100G Ethernet MAC & PCS
+ RS-FEC

Key Features and Benefits

1, 10, 25, 40/100G

  • Configurable statistics vector and collector on transmit and receive MAC/PCS data

  • Programmable Tx and Rx path VLAN detection

1, 10, 25, 40/100G

  • Soft PCS logic interfacing to standard serial transceiver at 1.25Gbps (1G), 10.3125Gbps (10, 40G), 25.78125Gbps (25, 100G)

  • Highly optimized implementation resulting in ultra-low latency and very low gate count

1, 10G

  • Compliant with the IEEE 802.3-2012 High Speed Ethernet Standard

25G

  • Fully compliant with IEEE802.3by-2016 and 25/50G thernet Consortium

  • Pre-compilation setting to include or not RS-FEC option (MAC/PCS/PMA or MAC/PCS/PMA + RS-FEC)

40/100G

  • Fully compliant with IEEE 802.3-2015 standard

  • Built-In Reed Solomon FEC RS(528, 514) with FEC bypass and error correction bypass capabilities

  • Two other versions of the IP core are also available, each supporting a single rate, i.e. 40Gbps or 100Gbps (with RS-FEC)

Download to get additional info

We’ll provide you with a free 30-day evaluation license allowing you to simulate and also test the core on a hardware platform.

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Ultra-low latency, high-speed, flexibility and scalability

BEst-in-class performance
in all categories

Our highly optimized IP cores are the top choice for data centers, networking and communications equipment. 

The high-performance Ethernet MAC & PCS IP cores are based on a unified Verilog code solution that scales from 1-Gbps to 100-Gbps data rates. The cores optionally include Reed Solomon FEC RS (528, 514, 10) with FEC bypass and error correction bypass capabilities.

Our unique differentiators:

Ultra-low latency performances, ultra-low gate count & resources utilization

Unified code solution supporting multiple rates, 1-, 10-, 25-, 40- and 100-Gbps

Fully integrated MAC, PCS, and optionally RS-FEC solutions

High timing margin of > 20% on mid-speed grade FPGA devices

High scalability and flexibility where same code and documentation is valid for all rates

Fully configurable statistics vector and collector on MAC, PCS, and RS-FEC

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FAQ

WE LIKE SIMPLICITY AND TRANSPARENCY

What is your business model?

We license semiconductor IP cores and provide design services. For IP cores, we typically charge an upfront license fee which is invoiced when the product is delivered.

Do you have a reference in design?

Yes. We have a few FPGA reference designs (Xilinx and Intel PSG) that we can provide to help you integrate the cores in your design.

What licensing models do you support?

Our licensing models are based on common set of terms known as the SignOnce IP License. We offer project and site licensing options.

Do you provide support?

Technical support and updates are included in the first year after delivery of the IP cores. It’s generally via email and conference calls. It is also possible to extend the support, updates and maintenance period.

Minimize time-to-market with our implementation expertise and support

We can easily customize our products to meet your needs by combining different speeds and options specifically adapted to your applications.

Case Study

Multinational Investment Bank 
Ethernet IP Cores

Orthogone developed this line of products for applications such as algorithmic trading, market data feed handlers and Tick-to-Trade platforms where latency is critical.

Read our product case study
High Performance Ethernet MAC & 
PCS + RS-FEC
Our rich set of standard and advanced features 
ideal for a large number of applications
These FPGA/ASIC IP cores are designed using advanced techniques leading to ultra-low gate count utilization and amazing latency performances.


The high-performance Ethernet MAC & PCS IP cores are based on a unified Verilog code solution that scales from 1-Gbps to 100-Gbps data rates. The cores optionally include Reed Solomon FEC RS (528, 514, 10) with FEC bypass and error correction bypass capabilities.

Best-in-class performances in all categories and include some unique differentiators :
  • Significant improvement in gate count and resource utilization performances
  • Ultra-low wire-to-wire latency for all options
  • Unified code solution supporting multiple rates, 1-, 10-, 25-, 40- and 100-Gbps
  • Fully integrated MAC, PCS, and optionally RS-FEC solutions
  • High timing margin of > 20% on mid-speed grade FPGA devices
  • High scalability and flexibility where same code and documentation is valid for all rates
  • Fully configurable statistics vector and collector on MAC, PCS, and RS-FEC
Explore with us
We can discuss your project requirements together.

Our eco-system technology partners

Distributor for Asian markets

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Our location

200-1425 Trans-Canada Highway
Dorval, Québec, Canada
H9P 2W9

So, what's your challenge?

So, what's your challenge?

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