Hardware Acceleration & HPC

Ultra-low latency and gate count Ethernet MAC/PCS and RS-FEC IP Cores

The Challenge

Develop ultra-low latency and ultra-low gate count Ethernet MAC/PCS and RS-FEC IP Cores for applications where latency is critical such as algorithmic trading.

Client: Investment Banks & HFT Firms

Location: Worldwide

Cores must be capable of addressing typical applications such as:

Market Data Feed Handler and Tick-to-Trade Platforms
Ethernet Network Test Appliances
Network Security Appliances
High Performance Computing

This is how we do it

Orthogone used a holistic approach to develop multiple flavors of the Ethernet MAC/PCS to support multiple data rates and Forward Error Correction (FEC) options. A single Verilog source code platform was used to support all configurations, options and technology process nodes. This greatly simplified test, integration and regression and preserved a uniform design for all options and configurations.

Multiple design innovations in the data processing algorithms resulted in ultra-low gate count and amazing latency performances making the cores ideal for applications where latency is critical (e.g. algorithmic trading).

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