Develop ultra-low latency and ultra-low gate count Ethernet MAC/PCS and RS-FEC IP Cores for applications where latency is critical such as algorithmic trading.
Client: Investment Banks & HFT Firms
Location: Worldwide
Orthogone used a holistic approach to develop multiple flavors of the Ethernet MAC/PCS to support multiple data rates and Forward Error Correction (FEC) options. A single Verilog source code platform was used to support all configurations, options and technology process nodes. This greatly simplified test, integration and regression and preserved a uniform design for all options and configurations.
Multiple design innovations in the data processing algorithms resulted in ultra-low gate count and amazing latency performances making the cores ideal for applications where latency is critical (e.g. algorithmic trading).
Multiple deployments have been made for different market segments and geographic locations.
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200-1425 Trans-Canada Highway
Dorval, Québec, Canada
H9P 2W9
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1 (514) 316-1917So, what's your challenge?
